There is a wide commercial market available for the use of electronic real time clocks which maintain the current date and time while powered by batteries. One significant feature requirement of this market is very low battery power consumption by the crystal oscillator used to generate the time base for the real time clock circuitry. One technique used in current devices is a CMOS inverting amplifier operating in the weak inversion regime of MOSFET transistors.
CMOS crystal oscillators which use inverting amplifier configurations require some form of negative DC feedback in order to maintain a stable DC operating point for the oscillator amplifier to function properly.
In particular, these crystal oscillator configurations require both a P-channel (PCH) and an N-channel (NCH) MOS devices configured for complementary amplification, VCC power and GND ground connections, a crystal resonator (typically an external component to the amplifier circuitry), two crystal load capacitors (to trim the crystal resonant frequency), a feedback resistor to provide negative gain feedback for the amplifier, a current limiting resistor to limit the power dissipation of the crystal, and a complementary MOS amplifier to buffer the output of the crystal oscillator amplifier (See FIG. 1).
Current crystal oscillators often limit the voltage amplitude across the crystal to approximately 1.5 V, with internal supply voltages for the crystal oscillator being set to approximately 1.7 V-2.0 V.
Many current crystal oscillators use an integrated resistor as the feedback resistance for the inverting CMOS amplifier mentioned above. Occasionally, a CMOS transmission gate operating in the linear region is used to simulate a resistor for the required feedback resistance. In this mode the resistance of the CMOS transmission gate can be considered constant to a first order approximation, as the gate-source voltage is above the threshold voltage of approximately 0.8 V-1.2 V for either the P-channel or the N-channel device.
A T-type resistor/capacitor combination can also be used to implement the feedback network, the advantage of this approach being the reduction of negative feedback at the operating frequency of the crystal oscillator, while at the same time providing significant negative feedback at DC to ensure a stable input bias point to the CMOS amplifier.
A problem with current crystal oscillators can be observed when either noise or DC leakage causes the input to the inverting oscillator amplifier to drift from its nominal DC bias point. The source of this noise or DC leakage can be either capacitive coupling or poor printed circuit board cleaning which may leave minute conductive residue between the amplifier input node and some other portion of the oscillator circuitry.
As a result of this leakage path, currents on the order of 5-50 nA may be injected or extracted from either the input or the output of the oscillator amplifier, resulting in a change in the bias point of the oscillator amplifier. As the bias point shifts, the gain and frequency stability of the crystal oscillator system suffer significantly.
Eventually, with a significantly high leakage path, the overall loop gain of the amplifier falls below unity and oscillation ceases. This leakage threshold is termed the "input leakage sensitivity" and the "output leakage sensitivity" for the oscillator amplifier input and output respectively, and is usually expressed as a positive/negative pair of numbers which represent the amount of current that can be sinked by the oscillator pin as well as sourced by the same pin.
As discussed above, current crystal oscillator implementations suffer in that they have very low leakage sensitivity values, typically in the range of 2-10 nA on an oscillator running on a 3 V battery using approximately 300 nA current.
The use of lower resistive feedback could be used to improve the leakage sensitivity; however, this reduces the overall oscillator amplifier gain at the target frequency of the system. As a general rule, greater negative feedback reduces the overall system gain and simultaneously increases the bias point stability.
While T-type resistive/capacitor filter networks have been used in discrete oscillator amplifiers, they suffer from loading and device sizing problems when implemented in integrated form. This is due to the large area required for large value resistors and the large capacitance present in large value resistors when integrated on a silicon substrate.
A significant aspect of the leakage sensitivity present within current designs is due in part to changes in packaging technology. Within the past decade, there has been a significant migration from 100-mil centered thru-hole dual in-line (DIP) packages to surface mount technologies.
This migration to surface mount technology has in general significantly reduced the inter-pin spacing dimensions on a given device package configuration. For example, in 1985 a standard real time clock comprised a 100-mil spaced, 16-pin DIP package mounted on a circuit board with a 32768 Hz crystal mounted beside the package. Ten years later, the same configuration would have the real time clock packaged in a 16-pin SOIC or TSSOP with inter-pin spacings of 50-mils or 25-mils.
Given similar printed circuit board (PCB) contamination levels, this would result in one-half to one-quarter the inter-pin resistance in the surface mount technology as compared to the previous thru-hole technology.
This reduction in resistance results in a direct linear increase in inter-pin leakage, making the new surface mount technology two to four times more susceptible to leakage than the previous thru-hole technology. This analysis of reduced leakage immunity assumes that the board cleaning technology has remained constant during the move to surface mount technology. This is not the case, however, as the removal of environmentally unfriendly CFC-based PCB cleaning solutions has resulted in the substitution of many PCB cleaning agents which do not perform at the same level as their CFC-based counterparts. This results in more contamination and leakage than would have been expected using a conventional CFC-based cleaning agent.
Especially vulnerable to leakage paths are the new water-based cleaning agents, which can produce humidity-sensitive "spider hair" leakage trails on PCBs which can appear open at low humidity levels and have 100 megohms of impedance or less under high humidity conditions. It is important to remember that 1 gigaohm impedance using the current oscillator technology represents more than 1 nA of leakage current. If this figure is multiplied by four to account for surface mount technology, then the total leakage level is 4 nA. This figure is in many cases more than can be tolerated by the existing oscillator bias stabilization schemes.
Thus, it can be readily seen that with changes in packaging technology and PCB cleaning technology, the same circuit designs which were adequate in the 1985 timeframe can and in fact do fail to address significant design issues present 10 years later.
The techniques using static resistors or transmission gates in their linear or near-linear regions of operation fail to address the desirability of a dynamic feedback resistance characteristic which varies with frequency, operating voltage, and current bias point.
Another problem with current technologies is the frequency deviations of the crystal oscillator which are caused by shifts in bias point of the system. Minute shifts in the operating bias point cause shifts in the resonant frequency of the oscillator due to voltage coefficients associated with the trim capacitors in the oscillator amplifier.
Yet another issue of concern with the current amplifier topologies used in real time clock crystal oscillators is that of noise immunity. Since the CMOS inverting amplifier is running on very low currents (less than 1 uA at 3 V), external noise may be injected into either the input or the output of the CMOS amplifier and impact the oscillation frequency of the crystal oscillator.
Attempts to solve some of these problems have in the past taken the form of the addition of resistive or semi-resistive negative feedback to the CMOS oscillator amplifier. While this approach allows the bias point and noise issues to be addressed, it suffers significantly in the fact that it reduces the closed-loop gain of the oscillator amplifier at the target crystal frequency, which is typically on the order of 32768 Hz.
In conventional amplifiers, it is usually possible to increase the gain of the amplifier by the judicious use of more operating power. However, since one of the primary design goals of battery-powered real time clocks is that of low power consumption, there is a limit to the extent to which this approach may be used to solve the reduction of gain caused by the addition of negative feedback.
What exacerbates the problem in the case of real time clock oscillators operating in the weak inversion regime is the dramatic loss of frequency response when operating at these low current levels. At 32768 Hz, the open loop gain may only be on the order of 5 or 10, meaning that any significant loss of gain due to negative feedback could cause the amplifier gain to be reduced below unity, forcing the oscillator to cease functioning. Since a good margin of closed loop gain is on the order of 4-8, significant use of negative feedback should be viewed with caution in this application.